Aspects of the present invention are directed to semiconductor characterization. More specifically the present invention is directed to an apparatus, system and method for parallel and independent electrical characterization of a plurality of MOSFET devices with sub-millisecond (msec) time resolution.
As semiconductor manufacturing decreases the size of the components on a wafer the number of components increases exponentially. As a result the number of components requiring testing per wafer has also increased. This may cause the test station to become a choke point in the manufacture of wafers. Therefore there is a need for a method, system and apparatus that permits testing of components at an increased rate. The alternative is for the percentage of components tested to be reduced potentially affecting the quality assurance of the line.
Traditionally, electrical characterization of semiconductor devices (including inline and offline characterization of device parametrics and reliability) involves an extended matrix of test/stress conditions, and a reasonable sample size (e.g. 5 devices) for each condition is required for statistics. Such characterization is usually performed using a rack of electronics (including precision voltage sources, DVM's, a switch matrix, etc.) controlled by a central computer.
In the case of wafer-level characterization, such test/stress is carried out using wafer probe stations where the semiconductor device(s) and the rack of test equipment is electrically couple through a set of probes. In the case of long-term (e.g. longer than a week) reliability characterization where it is not practical to use probe stations due to the huge time consumption, such test/stress is conducted by a module-level system where semiconductor devices from a plurality of silicon dies are electrically connected to the rack of test equipments through wire-bonding to a substrate which is plugged into a test socket.
Note, however, that in both wafer-level and module-level cases described above, the test/stress condition is set by the test equipment attached to the probe set(s) (for wafer-level) or module(s) (for module-level). Therefore, the matrix of test/stress conditions need to be carried out one at a time (in serial), which significantly hinders the efficiency of characterization. Thus to accomplish the number of tests a design or quality engineer needs to run may take more time than is available or severely delay the delivery of parts. Another result may be to scale down the number of tests, potentially resulting in lower quality parts.
Furthermore, it is becoming critical in recent advanced semiconductor technologies for very fast characterization (sub-msec) time resolution. As an example, certain semiconductor degradation mechanism (e.g. BTI, or bias temperature instability of MOSFET devices) shows fast recovery, which makes it challenging to accurately capture the electrical shift under test mode after removing the stress condition. Prior art characterization of multiple semiconductor devices is performed in a sequential approach using a switch matrix, and thus it is not possible to perform such fast characterization.